Where is ready cfw for ps3 4k
cfw can I install on my ps3 super slim cech-4011B???
If it could, this will replace many modchip.. The project is much awaited by many people, it will make a ps3 super slim looks like a fat and slim, works to play games no need of a modchip... ps3oon.
PS3 XDR DRAM Project by ModRobert Continues, Logic Analyzer Findings
Following his previous updates on the PS3 4K dump project which aims as enabling PlayStation 3 CFW on a PS3 Super Slim console, modrobert has posted an update recently dubbed the PS3 XDR DRAM adventure continues.
Below are the details, to quote: After removing the XDR DRAM wiring completely, the PS3 still kept on shutting down with three beeps and blinking red light. Also removed the E3 flasher thinking the wiring might have gone bad, still same problem, kept shutting down randomly.
Was then struggling with the notion that my custom interface damaged the XDR DRAM permanently somehow, but after searching around these shutdown problems seemed to match YLOD (Yellow Light Of Death), so did a reflow with heat gun and it worked!
Also got a logic analyzer (combined with oscilloscope) now which can handle these speeds and you can set threshold voltage levels which will come in handy.
So going in for round two; weird wiring vs XDR DRAM - FIGHT!
I have soldered a new XDR DRAM interface in my old reflowed friend; the fat PS3 with CFW, and played around with the logic analyzer to find the optimal voltage levels to dump the RSL and CMOS 1.8V traffic.
This is what the whole waveform looks like, from PS3 power-on, all the serial XDR DRAM traffic happens during a brief period of 12.99 ms, then stops long before XMB is completely loaded.
First there is an init session (perhaps just circuits getting powered up), then a reset session, and then it ends with two clusters of signals including serial write commands (the CMD signal).
This is the XDR DRAM reset sequence.
Here is an example of a complete command transaction, around 30 clock cycles (SCK).
Next up is identifying each of these individual serial commands and document that.
Forgot to add the full state listing from the logic analyzer, it is attached now.
You were right about the frequency, looks like SCK is just over 40 MHz (41.666666666667) for the commands, full cycle at 24 ns.
The SCK frequency during reset is much slower though, each pulse width is still 12ns, but the time between pulses is longer, full cycle is 404ns (~2.5 MHz).
More PlayStation 3 News...
is there any chance to install cfw on ps3 super slim?
No chance at all.
this is a one step closer to the cfw on superslim that we are waiting.
It is becoming more interesting!